The DRAM array of claim 1, wherein the work function for the dummy word lines is approximately 4. The DRAM array of claim 1, wherein the dummy word lines are coupled to a negative potential with respect to a substrate potential. The DRAM array of claim 1, wherein the bit line is a metal line disposed above the pairs of cells in the array. The DRAM array of claim 1, wherein the capacitors are disposed above the bit lines.
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You Be the Judge.. My colleague at Chipworks , Randy Torrance, popped the lid to take a look, and drafted the following discussion which, amongst other things, raises the perennial question for us reverse engineers - how do you define a process node in real terms? Now read on.. The first thing we did was measure the die size. Clearly this 2 Gb die is much smaller than 2X the nm 1 Gb die, so our assumption that we have a 3x nm part looks good so far.
We were surprised with what we found. The capacitors are laid out in a square array instead of the more usual hexagonal pattern see below , and the wordline WL and bitline BL pitches are both about 96 nm. That places this DRAM at the nm process node, the same as the previous Samsung generation of 48 nm. So why does the die size look like it should be a smaller technology? For this we need to look at cell size.
This allows for the use of a folded bitline architecture, which helps reduce noise. In order to decrease cell area, companies came out with the first 6F2 cells in ; this 6F2 architecture is now used by all major players in the DRAM market. Clearly this cell is much smaller than the 48 nm generation.
If we take the half-WL pitch as the minimum feature size F , we get an F of 48 nm for this process. The cell area of 0. From this point of view it certainly appears so. The cell is four times the size of the minimum feature, squared. But, there are other ways of looking at this. A 4F2 architecture is defined as having a memory cell at each and every possible location, that being each and every crossing of WL and BL, with the cell being 2F x 2F.
The images are shown below. As can be seen, both have very similar layouts. The angle of the active silicon diffusion direction is about the same. The active areas are ovals. Each diffusion has two wordlines crossing it. There is a gap between all the active areas, such that a third WL does not cross active on this diagonal active direction. In both cases the wordlines do not have a transistor under them at every possible location that a transistor would fit.
Rather, one of every three possible transistor locations is filled with a break in the diffusion stripe. As we noted above, a 4F2 cell really should have transistors at every possible transistor location.
So if you take half the minimum pitch in the chip as the node, this is a nm part ITRS still defines F as half the contacted M1 pitch, which would be 48 nm. So, do we have a 32 nm node, and a 6F2 architecture? The only issue is that if we use 32 nm as F, then when we plug that into the 6F2 equation we get 0. However, the cell size is actually 0. So… do we call this a 32 nm or a 39 nm node? Samsung have had to put in a few process tweaks to squeeze the cells into the much smaller area, mostly at the transistor and STI level.
FIELD OF THE INVENTION
In one illustrative embodiment, a memory array having a plurality of memory cells having an effective size of 6F2 is disclosed which has a plurality of dual bit active areas, each of the active areas having a substantially longitudinal axis, and a plurality of digitlines on a 3F-pitch arranged in a folded digitline architecture, wherein the active areas are positioned such that the longitudinal axis of the active areas is oriented at an angle with respect to a centerline of the digitlines. Description of the Related Art Memory devices are typically provided as internal storage areas in the computer There are several different types of memory. One type of memory is random access memory RAM that is typically used as main memory in a computer environment. Most RAM is volatile, which means that it requires a steady flow of electricity to maintain its contents. A dynamic random access memory DRAM is made up of memory cells.
6F2 buried wordline DRAM cell for 40nm and beyond
And they are in volume production, we have also found them in a point and shoot camera. Therefore, in the above structure, the semiconductor device having a height corresponding to the protruded portion of the metal gate electrode 20 is formed. Example embodiments relate to a semiconductor device having a buried gate electrode and a method of fabricating the same. The gate electrode layer may be formed of polysilicon. As illustrated, the gate electrode layer may be recessed to the same level as the buried word line In example embodiments, the buried word line may include any one selected from the group consisting of tungsten Waluminum Alcupper Cumolybdenum Motitanium Titantalum Taand ruthenium Ruor a combination thereof.
Tera Isolation between each cell pair and its neighboring cell pairs along a given bit line is obtained through isolation transistors, such as transistors 30 and 31 of FIG. The capacitor is formed in the ILD layers 3 and 4 for the illustrated embodiment. Please help improve this media file by adding it to one or more categories, so it may be associated with related media draj how? The array of claim 1, wherein the dummy word is coupled to a negative potential with respect to a substrate potential.